device-tree bindings for Phytium Display Controller

Display controller is used to transfers the image data from a video memory
buffer to output interface.

Required properties:
- compatible: value should be "phytium,dcFTD330"/"phytium,dc9x00".

- reg: host interface and display physical base address and length.

- interrupts: interrupt which controller used.

- clocks: must include clock specifiers corresponding to entries in the
		clock-names property.

- clock-names: Must contain
		core_clk: core clock.
		pix_clk: pixel clock for output stream.
		axi_clk: axi clock for data fetch.

- iommus: iommu node

- port: A port node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt.

Example 1:

dcFTD330@0xf6f00000 {
	compatible = "phytium,dcFTD330";
	reg = <0xf6f00000 0x100>, <0xf6f00800 0x2000>, <0xf7010000 0x1000>;
	interrupts = <22>;
	clocks = <&vout_clk>, <&disp_clk>, <&axi_clk>;
	clock-names = "core_clk", "pix_clk", "axi_clk";
	iommus = <&dcmmu>;

	port {
		#address-cells = <1>;
		#size-cells = <0>;
		dc_out_dpi0: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&hdmi_input>;
		};
		dc_out_dpi1: endpoint@1 {
			reg = <1>;
			remote-endpoint = <&vd_input>;
		};
	};
};

Example 2:

dc9400@90c0000 {
	compatible = "phytium,dc9x00";
	reg = <0x0 0x90c0000 0x0 0x200000>;
	interrupts = <0x0 0x0b 0x4>;
	interrupt-names = "dc9400_irq";
	clocks = <&vout_clk>, <&disp_clk>, <&axi_clk>;
	clock-names = "core_clk", "pix_clk", "axi_clk";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		dc_out_0: port@0 {
			reg = <0>;
		};
		dc_out_1: port@1 {
			reg = <1>;
		};
		dc_out_2: port@2 {
			reg = <2>;
		};
		dc_out_3: port@3 {
			reg = <3>;
		};
		dc_out_4: port@4 {
			reg = <4>;
		};
	};
};